Channel Link Bit Assignments
Camera Link Base/Medium/Full Configurations
Each channel link receiver provides 28 bits to the frame grabber. The following table shows the bit assignments of the 3 channel link receivers X, Y, and Z in the case of a Camera Link Full configuration (as defined by the Camera Link 1.1 standard).
Channel link pin name |
Channel link X signal name |
Channel link Y signal name |
Channel link Z signal name |
RxCLKOut |
PClk_X |
PClk_Y |
PClk_Z |
RxOUT 0 |
Port A0 |
Port D0 |
Port G0 |
RxOUT 1 |
Port A1 |
Port D1 |
Port G1 |
RxOUT 2 |
Port A2 |
Port D2 |
Port G2 |
RxOUT 3 |
Port A3 |
Port D3 |
Port G3 |
RxOUT 4 |
Port A4 |
Port D4 |
Port G4 |
RxOUT 5 |
Port A7 |
Port D7 |
Port G7 |
RxOUT 6 |
Port A5 |
Port D5 |
Port G5 |
RxOUT 7 |
Port B0 |
Port E0 |
Port H0 |
RxOUT 8 |
Port B1 |
Port E1 |
Port H1 |
RxOUT 9 |
Port B2 |
Port E2 |
Port H2 |
RxOUT 10 |
Port B6 |
Port E6 |
Port H6 |
RxOUT 11 |
Port B7 |
Port E7 |
Port H7 |
RxOUT 12 |
Port B3 |
Port E3 |
Port H3 |
RxOUT 13 |
Port B4 |
Port E4 |
Port H4 |
RxOUT 14 |
Port B5 |
Port E5 |
Port H5 |
RxOUT 15 |
Port C0 |
Port F0 |
- |
RxOUT 16 |
Port C6 |
Port F6 |
- |
RxOUT 17 |
Port C7 |
Port F7 |
- |
RxOUT 18 |
Port C1 |
Port F1 |
- |
RxOUT 19 |
Port C2 |
Port F2 |
- |
RxOUT 20 |
Port C3 |
Port F3 |
- |
RxOUT 21 |
Port C4 |
Port F4 |
- |
RxOUT 22 |
Port C5 |
Port F5 |
- |
RxOUT 23 |
Spare_X |
Spare_Y |
Spare_Z |
RxOUT 24 |
LVAL_X |
LVAL_Y |
LVAL_Z |
RxOUT 25 |
FVAL_X |
FVAL_Y |
FVAL_Z |
RxOUT 26 |
DVAL_X |
DVAL_Y |
DVAL_Z |
RxOUT 27 |
Port A6 |
Port D6 |
Port G6 |
Notes
- The bit assignments of Channel Link receiver X for the Full configuration are also applicable to the Base and Medium configurations.
- The bit assignments of Channel Link receiver Y for the Full configuration are also applicable to the Medium configurations.
- When the board is used in Base configuration, it ignores all the signals delivered on Channel Link receivers Y and Z.
- When the board is used in Medium configuration, it ignores all the signals delivered on Channel Link receiver Z.
- The four enable signals, FVAL, LVAL, DVAL, and Spare, are replicated on all channel links.
- The camera clock signal is also replicated on all channel links
Camera Link 80-bit Configuration
Each channel link receiver provides 28 bits to the frame grabber. The following table shows the bit assignments of the 3 channel link receivers X, Y, and Z for 80-bit channel link configuration (as defined by the Camera Link 2.0 standard).
Channel link pin name |
Channel link X signal name |
Channel link Y signal name |
Channel link Z signal name |
RxCLKOut |
PClk_X |
PClk_Y |
PClk_Z |
RxOUT 0 |
Port A0 |
Port D2 |
Port G5 |
RxOUT 1 |
Port A1 |
Port D3 |
Port G6 |
RxOUT 2 |
Port A2 |
Port D4 |
Port G7 |
RxOUT 3 |
Port A3 |
Port D5 |
Port H0 |
RxOUT 4 |
Port A4 |
Port D6 |
Port H1 |
RxOUT 5 |
Port A5 |
Port D7 |
Port H2 |
RxOUT 6 |
Port A6 |
Port E0 |
Port H3 |
RxOUT 7 |
Port A7 |
Port E1 |
Port H4 |
RxOUT 8 |
Port B0 |
Port E2 |
Port H5 |
RxOUT 9 |
Port B1 |
Port E3 |
Port H6 |
RxOUT 10 |
Port B2 |
Port E4 |
Port H7 |
RxOUT 11 |
Port B3 |
Port E5 |
Port I0 |
RxOUT 12 |
Port B4 |
Port E6 |
Port I1 |
RxOUT 13 |
Port B5 |
Port E7 |
Port I2 |
RxOUT 14 |
Port B6 |
Port F0 |
Port I3 |
RxOUT 15 |
Port B7 |
Port F1 |
Port I4 |
RxOUT 16 |
Port C0 |
Port F2 |
Port I5 |
RxOUT 17 |
Port C1 |
Port F3 |
Port I6 |
RxOUT 18 |
Port C2 |
Port F4 |
Port I7 |
RxOUT 19 |
Port C3 |
Port F5 |
Port J0 |
RxOUT 20 |
Port C4 |
Port F6 |
Port J1 |
RxOUT 21 |
Port C5 |
Port F7 |
Port J2 |
RxOUT 22 |
Port C6 |
Port G0 |
Port J3 |
RxOUT 23 |
Port C7 |
Port G1 |
Port J4 |
RxOUT 24 |
LVAL_X |
Port G2 |
Port J5 |
RxOUT 25 |
FVAL |
Port G3 |
Port J6 |
RxOUT 26 |
Port D0 |
Port G4 |
Port J7 |
RxOUT 27 |
Port D1 |
LVAL_Y |
LVAL_Z |
Notes
- Only two enable signals are delivered to the frame grabber: FVAL, and LVAL; DVAL and Spare are omitted.
- The LVAL signal is replicated on all channel links.
- The camera clock signal is also replicated on all channel links.