Camera Link Requirements
Each channel link is composed of 5 LVDS pairs:
- One LVDS pair transmits the clock to the frame grabber.
- Four LVDS pairs transmit the payload to the frame grabber at a bit rate equal to the clock frequency multiplied by 7.
Note. The Lite configuration uses a subset of the original channel link with 3 LVDS pairs i.o. 5: 1 for the clock, 2 for the data.
The following requirements apply to each channel link separately.
Clock Line Requirements
For each channel link individually, the clock signal must satisfy the following requirements:
- Clock frequency range: 20 to 85 MHz.
- The clock may not be switched off during normal operation.
- For correct operation of PoCL, it is mandatory to apply the clock as soon as possible after power on. The time-out delay is 500 milliseconds.
- The clock jitter must be as low as possible; it is recommended to use X-Tal oscillators to generate the Camera Link clock. It may not exceed 1 ns or 20% of the clock period.
- The clock duty cycle must be better than 25%/75%.
Data Lines Requirements
For each channel link individually, the electrical signal of the 4 data lines must be conform to the Camera Link requirements, namely be generated by a National Semiconductor chip as specified in the Table A-1 of the Camera Link Specification v1.1.
The Lite configuration uses a specific bit assignment for the two data lines. It conforms to the requirements of Camera Link 2.0 specification.
Cable Requirements
The camera cables must be Camera Link compliant and terminated with a MiniCL connector at the frame grabber side.
Both PoCL and non-PoCL cables can be used.
The usage of poor quality Camera Link cables may cause malfunction. This becomes critical for systems with a high clock rate or with long cables length. Therefore, Euresys recommends using Camera Link cables that are certified by the cable manufacturer for the length vs. clock rate combination.
Cameras using the Lite configuration must be connected using a 14-pin MiniCL to 26-pin MiniCL cable.