PCI Express Bus

Standard Compliance

This board implements a single-lane PCI Express end-point interface.

The PCI Express end-point interface is compliant with the PCI Express Card Electromechanical Specification, revision 1.1.

A PCI Express lane is composed of two unidirectional 2.5 Gigabits-per-second serial links.

Additional Information

For more information about PCIe busses, their performance and their usage, refer to the Euresys PCI Express technology note.