PCI Express Bus
PCI Identification
Grablink Full XR is identified on the PCI Express system as follows:
PCI Vendor ID |
0x1805 |
PCI Device ID (Normal mode) |
0x0310 (784) |
PCI Device ID (Recovery mode) |
0x0311 (785) |
PCI Sub-Vendor ID |
0x0000 |
PCI Sub-Device ID |
0x0001 |
Standard Compliance
This board implements a 4-lane PCI Express end point interface.
The 4-lane PCI Express end point interface is compliant with the PCI Express Card Electromechanical specification Rev. 1.1. A PCI Express lane is composed of two unidirectional 2.5 Gigabits per second serial links.
PCI Express Bus Compatibility
This board can be inserted in a PCI Express slot inside a PC. It is compliant with the PCI Express Base Specification 1.1.
- 4-lane PCI Express
- The PCIe edge connector is 4-lane wide. It operates at 2.5 GHz.
- This board can be used in any 4-lane or larger PCIe slot. The board can be installed in a 4-lane or 8-lane PCIe slot. It can be used in a 16-lane PCIe slot that is not reserved for a graphical board.
Lane Configuration
The 4-lane PCI Express end point interface implements lane reversal, which enables the logical reversal of lane numbers.
Lane configuration |
Physical lane 3 |
Physical lane 2 |
Physical lane 1 |
Physical lane 0 |
Four non-reversed lanes |
Logical lane 3 |
Logical lane 2 |
Logical lane 1 |
Logical lane 0 |
Four reversed lanes starting on lane 3 |
Logical lane 0 |
Logical lane 1 |
Logical lane 2 |
Logical lane 3 |
One non-reversed lane |
|
|
|
Logical lane 0 |
One non-reversed lane starting on lane 3 |
Logical lane 0 |
|
|
|
During the configuration of the PCI Express fabric, the PCI Express end point interface negotiates the link width.
The negotiated link width is reported through the PCIeLinkWidth parameter.
The PCI Express end point interface supports two values of link width: 1 and 4.
The width of 4 is selected when the board is plugged into a slot a having one of the two supported 4-lane configuration. In any other case, the selected width is 1.
Payload Size
During the configuration of the PCI Express fabric, the PCI Express end point interface negotiates the payload size of the TLP packets. The maximum payload size of the end point interface is 1024 bytes.
The negotiated payload size is reported through the MultiCam parameter PCIePayloadSize.
64-bit Addressing Bus Master
The PCI Express end point interface supports 64-bit addressing for bus master access.
PCIe Endpoint Interface Revision Number
The revision number of the PCI Express end point interface is reported through the MultiCam PCIeEndpointRevisionID parameter.
PCI Express Bus Power Supplies
This board draws power exclusively from both the +3.3 and +12V rails of the PCI Express connector.
Parameter |
Min |
Typ |
Max |
Units |
PCI Express +3.3V supply voltage |
3.0 |
3.3 |
3.6 |
V |
PCI Express +3.3V supply current |
|
1.0 |
|
A |
PCI Express +12V supply voltage |
11.0 |
12 |
13.0 |
V |
PCI Express +12V supply current |
|
0.41 |
|
A |
PCI Express power rail requirement |
|
8.2 |
9.9 |
W |
- The typical supply current values are measured during normal board operation at 25°C ambient temperature and nominal supply voltages.
- The maximum current on each supply rails are below the limits allowed for a 10W slot.
- The power consumption is below the 25W maximum power dissipation allowed for a x4 PCI Express add-in card.
- Refer to Environmental for details on heat dissipation.
PCI Express Connector Pins Assignments
Pin # |
Side B Name |
Side A Name |
1 |
+12V |
nPRSNT1 |
2 |
+12V |
+12V |
3 |
+12V |
+12V |
4 |
GND |
GND |
5 |
- |
- |
6 |
- |
TDI |
7 |
GND |
TDO |
8 |
+3V3 |
- |
9 |
- |
3V3 |
10 |
- |
3V3 |
11 |
nWAKE |
nPERST |
KEY |
KEY |
KEY |
KEY |
KEY |
KEY |
12 |
- |
GND |
13 |
GND |
REFCLK+ |
14 |
PETp0 |
REFCLK- |
15 |
PETn0 |
GND |
16 |
GND |
PERp0 |
17 |
- |
PERn0 |
18 |
GND |
GND |
19 |
PETp1 |
- |
20 |
PETn1 |
GND |
21 |
GND |
PERp1 |
22 |
GND |
PERn1 |
23 |
PETp2 |
GND |
24 |
PETn2 |
GND |
25 |
GND |
PERp2 |
26 |
GND |
PERn2 |
27 |
PETp3 |
GND |
28 |
PETn2 |
GND |
29 |
GND |
PERp3 |
30 |
- |
PERp3 |
31 |
nPRSNT2 |
GND |
32 |
GND |
- |
Additional Information
For more information about PCIe busses, their performance and their usage, refer to the Euresys PCI Express technology note.