MultiCam Boards Documentation > GRABLINK series Documentation > GRABLINK Quickpack CFA Handbook > Connector Specifications > System Connectors > ISOA1, ISOA2 Isolated Input/Output Ports > Introduction

Introduction

This isolated I/O port has the following characteristics:

Isolated I/O Port Schematic

Isolated I/O port ISOXn equivalent schematic

Note. I5V stands for Isolated 5 Volt.

The isolation barrier is composed with:

The 74HC14 is a HCMOS 5V device that implements a Schmitt-trigger input with hysteresis. It senses the voltage on the ISOXn through a 1.5 kΩ series resistor; it is protected against over voltage by Schottky diodes D1 and D2.

T1 connects ISOXn to I5V, forcing the ISOXn port to a HIGH level.

T2 connects ISOXn to IGND, forcing the ISOXn port to a LOW level.

T3 connects the chain of 1.5 kΩ and 510Ω resistors to IGND. This enables a 2 kΩ pull-down resistor on ISOXn and a 1/4 voltage divider in the input sense circuit.

T4 connects the 3 kΩ resistor to I5V, enabling a 3 kΩ pull-up on ISOXn.

The control logic turns on one transistor at a time which leads to four possible "states" of the electrical circuit. The default state is State U (Pull Up). The circuit resets to default state at power-on or when the FPGA device is cleared.

Four states of the electrical circuit

State U (Pull Up)

State H (Force High)

State U (Pull Up)

State H (Force High)

State D (Pull Down)

State L (Force Low)

State D (Pull Down)

State L (Force Low)