Open Collector Digital Output Mode
To be used as open collector digital output, the circuit is either in State U (Pull Up) or in State L (Force Low) according to the applied digital level:
Applied digital level |
Output State |
HIGH |
State U (Pull Up) |
LOW |
State L (Force Low) |
A state transition from State U (Pull-Up) occurs when setting IOC output mode after power ON or FPGA boot sequence.
In State U (Pull Up), the output is tied to the I5V through a 3 kΩ pull-up resistor.
Multiple open collector digital outputs can be tied together.
Open collector digital output state