Rate Divider
The rate divider circuit generates a line trigger signal at a frequency that is an integer fraction 1/N of the frequency of the pulses delivered by the quadrature decoder circuit.
For N consecutive incoming pulses issued by the quadrature decoder circuit, the 1/N rate divider:
- generates one output pulse (one line trigger)
- skips N-1 input pulse
The rate divider is initialized at the beginning of every MultiCam acquisition sequence. The first output pulse is produced from the first clock input pulse occurring after the sequence trigger event.
Beginning of an acquisition sequence for a value N of 4
The division factor N is user-programmable. Possible values of N include all integer numbers ranging from 1 up to 512, the default value is 1.
N is configured by the MultiCam parameter RateDivisionFactor.
Notes
- The output frequency is lower than (N > 1) or equal to (N = 1) the input frequency. It cannot be higher.
- The output pulse is generated immediately after a non-skipped input pulse. The line trigger pulses are phase-locked to the quadrature decoder output.
- The rate divider settings may not be modified while acquisition is in progress.